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DATASHEET
CLOCK DISTRIBUTION CIRCUIT Description
The IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or 1.8 V to 2.5 V LVCMOS input and generates four high-quality LVDS outputs, and two programmable divided outputs. It includes a redundant input with automatic glitch-free switching when the primary reference is removed. The primary input may be selected by the user by pulling the SEL pin low or high. If the primary input is removed and brought back, it will not be re-selected until 1024 cycles have passed. The IDT6T39007A specifically addresses the needs of handheld applications in both performance and package size. The device is packaged in a small 4mm x 4mm 24-pin QFN, allowing optimal use for limited board space.
IDT6T39007A Features
* * * * *
Packaged in 24-pin QFN TCXO sine wave input +2.5 V operating voltage Four buffered LVDS outputs Two programmable outputs for power control up to 3.0 V LVCMOS levels based on VDDO1/VDDO2
* Individual output enables controlled via I2C or OEx * Pb-free, RoHS compliant package * Industrial temperature range (-40C to +85C)
Block Diagram
VDD 2.5 V 3 SEL SCLK SDATA LVCMOS_INB OE1 OUT1 LVDS OE2 OUT2 LVDS OUT3 LVDS OUT4 LVDS VDDO1 PWRCTRL_CLK1 VDDO2 PWRCTRL_CLK2
TCXO_INA 100mVpp
MUX Divide Logic
2 GND
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Pin Assignment
TCXO_INA SEL LVCMOS_INB
SEL Pin Configuration Table
SEL
0
GND VDD
Primary Input
LVCMOS_INB TCXO_INA
VDDO1
1
OE Pin Configuration Table
PWRCTRL_CLK1 PWRCTRL_CLK2 SCLK SDATA VDDO2 VDD
1
Thermal pad connected to silicon substrate. Connect to ground plane.
19
OUT1 OUT1B OUT2 OUT2B OUT3
OEx
0 1
OUTx LVDS
Disabled Enabled
7
13
OUT3B
OUT4
GND
VDD
OUT4B
24- pin QFN
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pin Name
PWRCTRL_CLK1 PWRCTRL_CLK2 SCLK SDATA VDDO2 VDD GND VDD OUT4B OUT4
Pin Type
Output Output Input Input Power Power Power Power Output Output
OE2
OE1
Pin Description
Programmable power control output 1. See I2C table. Programmable power control output 2. See I2C table. I2C clock input. I2C data input. Connect to +3.0 V. Connect to +2.5 V. Connect to ground. Connect to +2.5 V. Buffered LVDS output. Outputs tri-state when disabled. Buffered LVDS output. Outputs tri-state when disabled. Output enable control for OUT2 LVDSpins. Internal pull-up resistor. See table above. Output enable control for OUT1 LVDSpins. Internal pull-up resistor. See table above. Buffered LVDS output. Outputs tri-state when disabled. Buffered LVDS output. Outputs tri-state when disabled. Buffered LVDS output. Outputs tri-state when disabled.
OE2 OE1
OUT3B OUT3 OUT2B
Input Input
Output Output Output
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Pin Number
16 17 18
Pin Name
OUT2 OUT1B OUT1 GND VDD LVCMOS_INB SEL TCXO_INA VDDO1
Pin Type
Output Output Output Power Power Input Input Input Power
Pin Description
Buffered LVDS output. Outputs tri-state when disabled. Buffered LVDS output. Outputs tri-state when disabled. Buffered LVDS output. Outputs tri-state when disabled. Connect to ground. Connect to +2.5 V. Connect to primary LVCMOS input INB. See table above. Select pin for primary inputs. See table above. Internal pull-up resistor. Connect to TCXO input. Connect to +3.0 V.
19 20 21 22 23 24
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General I2C Serial Interface How to Write:
* * * * * * * * * *
Controller (host) sends a start bit Controller (host) sends the write address D4(H) IDT clock will acknowledge Controller (host) sends the beginning byte location =N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X - 1 (see Note 2) IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit
How to Read:
* * * * * * * * * * * * * *
Controller (host) sends a start bit Controller (host) sends the write address D4(H) IDT clock will acknowledge Controller (host) sends the beginning byte location =N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address D5(H) IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock sends Byte N + X - 1 IDT clock sends Byte 0 through byte X (if X(H) was written to byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Read Operation Index Block Write Operation
Controller (Host) T WR starTbit WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte = N O O O Byte N + X - 1 ACK P stoP bit . X B Y T E ACK O O O ACK . ACK O O O N P X B Y T E Beginning Byte N O O O Byte N + X - 1 Data Byte Count = X RT RD Slave Address D4(H) Beginning Byte = N ACK IDT (Slave/Receiver) Controller (Host) T WR starTbit Slave Address D4(H) WRite ACK IDT (Slave/Receiver)
Repeat starT ReaD
ACK
Slave Address D5(H)
Not acknowledge
stoP bit
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I2C Address
The IDT6T39007A is a slave-only device that supports block read and block write protocol using a single 7 bit address and read/write bit. A block write (D4(H)) or block read (D5(H)) is made up of seven (7) bits and one (1) read/write bit.
A6 1
A5 1
A4 0
A3 1
A2 0
A1 1
A0 0
R/W# X
In applications where the indexed block write and block read are used, the dummy byte (bit 11-18) functions as a register-offset (8 bits) pointer.
Byte 0: Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved OE for OUT3 OE for OUT4 Reserved Reserved Reserved Reserved Type R R RW RW R R R R Power Up Condition Undefined Undefined 1 1 Undefined Undefined Undefined Undefined Output(s) Affected Not applicable Not applicable Notes
LVDS clock output LVDS clock output
Not applicable Not applicable Not applicable Not applicable
1=enabled 0=disabled 1=enabled 0=disabled
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Byte 1: Control Register
Bit 7 Description PWRCTRL_CLK1 Divider SEL bit 7 Type RW Power Up Condition 0 Output(s) Affected PWRCTRL_CLK1 Notes Default is /15 to get 866.666 kHz from 13 MHz Default is /15 to get 866.666 kHz from 13 MHz Default is /15 to get 866.666 kHz from 13 MHz Default is /15 to get 866.666 kHz from 13 MHz Default is /15 to get 866.666 kHz from 13 MHz Default is /15 to get 866.666 kHz from 13 MHz Default is /15 to get 866.666 kHz from 13 MHz Default is /15 to get 866.666 kHz from 13 MHz
6
PWRCTRL_CLK1 Divider SEL bit 6
RW
0
PWRCTRL_CLK1
5
PWRCTRL_CLK1 Divider SEL bit 5
RW
0
PWRCTRL_CLK1
4
PWRCTRL_CLK1 Divider SEL bit 4
RW
0
PWRCTRL_CLK1
3
PWRCTRL_CLK1 Divider SEL bit 3
RW
1
PWRCTRL_CLK1
2
PWRCTRL_CLK1 Divider SEL bit 2
RW
1
PWRCTRL_CLK1
1
PWRCTRL_CLK1 Divider SEL bit 1
RW
1
PWRCTRL_CLK1
0
PWRCTRL_CLK1 Divider SEL bit 0
RW
1
PWRCTRL_CLK1
Byte 2: Control Register
Bit 7 Description PWRCTRL_CLK2 Divider SEL bit 7 Type RW Power Up Condition 0 Output(s) Affected PWRCTRL_CLK2 Notes Default is /46 to get 282.6kHz from 13 MHz Default is /46 to get 282.6kHz from 13 MHz Default is /46 to get 282.6kHz from 13 MHz Default is /46 to get 282.6kHz from 13 MHz Default is /46 to get 282.6kHz from 13 MHz
6
PWRCTRL_CLK2 Divider SEL bit 6
RW
0
PWRCTRL_CLK2
5
PWRCTRL_CLK2 Divider SEL bit 5
RW
1
PWRCTRL_CLK2
4
PWRCTRL_CLK2 Divider SEL bit 4
RW
0
PWRCTRL_CLK1
3
PWRCTRL_CLK2 Divider SEL bit 3
RW
1
PWRCTRL_CLK1
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2
PWRCTRL_CLK2 Divider SEL bit 2
RW
1
PWRCTRL_CLK1
Default is /46 to get 282.6kHz from 13 MHz Default is /46 to get 282.6kHz from 13 MHz Default is /46 to get 282.6kHz from 13 MHz
1
PWRCTRL_CLK2 Divider SEL bit 1
RW
1
PWRCTRL_CLK1
0
PWRCTRL_CLK2 Divider SEL bit 0
RW
0
PWRCTRL_CLK1
Byte 3: Control Register
Bit 7 to 0 Description Reserved Type R Power Up Condition Undefined Output(s) Affected Not applicable Notes
Byte 4 through 5: Control Register
Bit 7 to 0 Description Reserved Type R Power Up Condition Undefined Output(s) Affected Not applicable Notes
Byte 6: Control Register
Bit 7 6 5 4 3 2 1 0 Description Revision ID bit 3 Revision ID bit 2 Revision ID bit 1 Revision ID bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 Type R R R R R R R R Power Up 0 0 0 0 0 0 0 1 Output(s) Affected Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Notes
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Applications Information External Components
A minimum number of external components are required for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01 F should be connected between VDD and GND as close to the device as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into IDT pin.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the IDT6T39007A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT6T39007A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Max Supply Voltage, VDD LVCMOS_INB, SCLK and SDATA Inputs All Other Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Peak Soldering Temperature 5V -0.5 V to +3.3 V
Rating
-0.5 V to VDD+0.5 V -40 to +85 C -65 to +150 C 125 C 260 C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Output Supply Voltage (VDDO1, VDDO2)
Min.
-40 +2.25 VDD
Typ.
+2.5 +3.0
Max.
+85 +2.75 +3.15
Units
C V V
DC Electrical Characteristics
Unless otherwise specified, VDD =2.5 V 10%, VDDO1 = VDDO2 = 3.0 V 5%, Ambient Temp. -40 to +85 C
Parameter
Operating Supply Voltage Output Supply Voltage Input High Voltage Input Low Voltage High-Level Output Voltage Low-Level Output Voltage Operating Supply Current
Symbol
VDD VDDO VIH VIL VOH VOL IDD
Conditions
VDDO1, VDDO2 SEL, OEx, LVCMOS_INB SCLK and SDATA SEL, OEx, LVCMOS_INB SCLK and SDATA IOH = -4 mA IOL = 4 mA No load, all outputs switching at 13 MHz All outputs disabled Single-ended clocks
Min.
+2.25 VDD 0.75xVDD 0.7xVDD
Typ.
+2.5 3.0
Max.
+2.75 3.15
Units
V V V
0.35xVDD 0.3xVDD 1.7 0.7 15 TBD 70 18
V V V mA mA mA
Short Circuit Current
IOS
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Parameter
Output Impedance Internal Pull-Up Resistance Input Capacitance
Symbol
ZO Rpu CIN
Conditions
All clock outputs, OEx=1 SEL, OEx All input pins
Min.
Typ.
15 500 6
Max.
Units
k pF
AC Electrical Characteristics - Single-Ended Outputs
Unless otherwise stated, VDD =2.5 V 10%, VDDO1 = VDDO2 = 3.0 V 5%, Ambient Temp. -40 to +85 C
Parameter
Input Frequency Variance Input Frequencies Time Switch Clock Inputs TCXO Input Swing Output Frequency Error Output Rise Time Output Fall Time Output Clock Duty Cycle Output Enable time Clock Stabilization Time from Power Up
Symbol
FIN
Conditions
LVCMOS_INB, TCXO_INA, Note 2 LVCMOS_INB, TCXO_INA, Note 3 TCXO_INA
Min.
12.6
Typ.
13
Max.
13.4 0.4
Units
MHz MHz s
80 100 0 1 1 45 50 900 1.5 1.5 55 1 3 10
mV ppm ns ns % ms ms
tOR tOF
20% to 80%, Note 1 80% to 20%, Note 1 Measured at VDDO/2, Note 1 OE goes high, output within 1% of final frequency Power up, output within 1% of final frequency
Note 1: CL = 8 pF. Note 2: Delta from 13 MHz. Note 3: By removing primary input and then bringing back primary input.
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AC Electrical Characteristics - LVDS Outputs
Unless otherwise stated, VDD = 2.5 V 10%, Ambient Temperature -40 to +85 C
Parameter
Differential Output Voltages | VOD | VOD Offset Voltage (VOS) Output CLock Duty Cycle VOS Output Short Circuit Current (IOS) Output Rise Time Output Fall Time
Conditions
RL = 100 VOD Magnitude Change Measured at VOS VOS Magnitude Change 20% to 80%, RL = 100 20% to 80%, RL = 100
Min.
250 -40 1.125 45
Typ.
350 0 1.25 50 3 -10 0.5 0.5
Max.
450 40 1.375 55 25
Units
mV mV V % mV mA
1.0 1.0
ns ns
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Parameter Measurement Information
VDD = 2.5V5%
Z = 50 LVDS Z = 50
Qx
SCOPE 50
80% 80% VOD
nQx
50
Clock Outputs
20% tOR tOF
20%
2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT RISE/FALL TIME
nCLK
VDD
CLK Pulse Width
out
DC Input
tPERIOD
LVDS
100
VOD/ VOD
out
tPW & tPERIOD
VOD SETUP
nCLK VOH
CLK t()
VOL
V DD
out
tjit() = t() - t()mean = Phase Jitter
DC Input
LVDS
out
50 50
V OS/ VOS
PHASE JITTER
VDD nCLK Cross Points CLK VOS GND VOD
V OS SETUP
DIFFERENTIAL INPUT LEVEL
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Marking Diagram
TBD
Notes: 1. "Z" is the device step (1 to 2 characters). 2. YYWW is the last two digits of the year and week that the part was assembled. 3. "$" is the assembly mark code. 4. "G" after the two-letter package code designates RoHS compliant package. 5. "I" at the end of part number indicates industrial temperature range. 6. Bottom marking: country of origin if not USA.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 2.5 m/s air flow
Min.
Typ.
29.1 22.8 21.0 41.8
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
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Package Outline and Package Dimensions (24-pin QFN)
Package dimensions are kept current with JEDEC Publication No. 95
Seating Plane Index Area N 1 2 A1 A3 (ND-1)x e (Ref) L N 1 2 Sawn Singulation Top View A E2 (Ref) ND & NE Even e (Typ) If ND & NE 2 are Even (NE-1)x e (Ref)
E
E2
2 b e D2 2 D2
D
(Ref) ND & NE Odd
Thermal Base
0.08 C
Symbol Min Millimeters Max
C
A A1 A3 b e N ND NE D x E BASIC D2 E2 L
0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC 24 6 6 4.00 x 4.00 2.3 2.55 2.3 2.55 0.30 0.50
Ordering Information
Part / Order Number
6T39007ANLGI 6T39007ANLGI8
Marking
TBD
Shipping Packaging
Tubes Tape and Reel
Package
24-pin QFN 24-pin QFN
Temperature
-40 to +85 C -40 to +85 C
"G" after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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